The present invention relates to integrated circuits having a FIFO memory with counters indicating input and output status from the FIFO.
FIFO memories are used in a number of integrated circuits for many different purposes. It is usually desirable to be able to track the status of data that has been input to or output from the FIFO. In one example, for a universal asynchronous receiver-transmitter (UART) data is sent through the FIFO and it is desirable to track the amount of data received by the FIFO and the data transmitted by the FIFO. The FIFO may be divided into a receive FIFO and a transmit FIFO which are separately monitored.
A typical UART chip, such as the industry standard 16C550, has a limited number of address pins, and thus a limited number of registers can be directly addressed. The 16C550 includes a general purpose register which can be used as a scratch-pad register or otherwise by the user.